This is the ninth edition of the CHERI instruction set architecture definition.

The document is available at the official repository as UCAM-CL-TR-987 or by local mirror here.


  author  = {Watson, Robert N. M. and Neumann, Peter G. and Woodruff,
            Jonathan and Roe, Michael and Almatary, Hesham and Anderson,
            Jonathan and Baldwin, John and Barnes, Graeme and Chisnall, David
            and Clarke, Jessica and Davis, Brooks and Eisen, Lee and Filardo,
            Nathaniel Wesley and Fuchs, Franz A. and Grisenthwaite, Richard
            and Joannou, Alexandre and Laurie, Ben and Markettos, A. Theodore
            and Moore, Simon W. and Murdoch, Steven J. and Nienhuis, Kyndylan
            and Norton, Robert and Richardson, Alexander and Rugg, Peter and
            Sewell, Peter and Son, Stacey and Xia, Hongyan},
  title   = {{Capability Hardware Enhanced RISC Instructions: CHERI
            Instruction-Set Architecture (Version 9)}},
  year    = {2023},
  month   = {sep},
  url     = {},
  institution={University of Cambridge, Computer Laboratory},
  number  = {UCAM-CL-TR-987}