Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 8) (2020)
=====================================================================================================
This is the eighth edition of the `CHERI
`_ instruction set
architecture definition. Relative to v7, this document has a significantly
updated abstract model (which includes capability compression, now no longer
seen as an approximation of the abstract model), more fully
describes CHERI-RISC-V, is synchronized with Arm's Morello prototype, and
includes significant discussion of micro-architectural aspects of CHERI.
My own contributions, for the curious, are mostly small and scattered across
the document, and were almost all jointly done with other co-authors.
Unsurprisingly, given my continued role as lead of the heap temporal safety
effort in CHERI/CheriBSD, most of my focus has been on features relevant to
that aspect of the system. These include the introduction of per-page
capability-load barriers (in section 3.10.3) and the associated portions of
the CHERI-RISC-V MMU capability control behaviors (5.3.10), an update to the
experimental composition of CHERI with memory versioning (e.g., Arm MTE;
D.6), documenting the experimental *ephemeral* capability mechanism for
richer revocable capability flow control (D.4), documenting the experimental
(but present in Arm's Morello) indirect sentries (D.9), and a modest
expansion of the historical context chapter (13).
The document is available at the official repository as
`UCAM-CL-TR-951 `_
or by local mirror :download:`here <2020-cheri-isav8.pdf>`.
BibTeX:
.. code-block:: none
@TechReport{watson:cheriisav8,
author = {Watson, Robert N. M. and Neumann, Peter G. and Woodruff,
Jonathan and Roe, Michael and Almatary, Hesham and Anderson,
Jonathan and Baldwin, John and Barnes, Graeme and Chisnall, David
and Clarke, Jessica and Davis, Brooks and Eisen, Lee and Filardo,
Nathaniel Wesley and Grisenthwaite, Richard and Joannou,
Alexandre and Laurie, Ben and Markettos, A. Theodore and Moore,
Simon W. and Murdoch, Steven J. and Nienhuis, Kyndylan and
Norton, Robert and Richardson, Alexander and Rugg, Peter and
Sewell, Peter and Son, Stacey and Xia, Hongyan},
title = {{Capability Hardware Enhanced RISC Instructions: CHERI
Instruction-Set Architecture (Version 8)}},
year = {2020},
month = {oct},
url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-951.pdf},
institution={University of Cambridge, Computer Laboratory},
number = {UCAM-CL-TR-951}
}